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LT5537 Wide Dynamic Range RF/IF Log Detector DESCRIPTIO
The LT(R)5537 is a wide dynamic range RF/IF detector, operational from below 10MHz to 1000MHz. The lower limit of the operating frequency range can be extended to near DC by the use of an external capacitor. The input dynamic range at 200MHz with 3dB nonlinearity is 90dB (from -76dBm to 14dBm, single-ended 50 input). The detector output voltage slope is nominally 20mV/dB, and the typical temperature coefficient is 0.01dB/C at 200MHz.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
FEATURES

Low Frequency to 1000MHz Operation 83dB Dynamic Range with 1dB Nonlinearity at 200MHz Sensitivity -76dBm or Better at 200MHz Log-Linear Transfer Slope of 20mV/dB Supply Voltage Range: 2.7V to 5.25V Supply Current: 13.5mA at 3V Tiny 8-Lead (3mm x 2mm) DFN Package
APPLICATIO S

Linear-to-Log Signal Level Conversion Received Signal Strength Indication (RSSI) RF Power Control RF/IF Power Detection Receiver RF/IF Gain Control Envelope Detection ASK Receiver
TYPICAL APPLICATIO
7k 7k
OPTIONAL
4 CAP+
5 CAP-
15nF RF IN 15nF 3 IN 2 IN
OFFSET CANCELLATION
+
VCC
6 1nF 1F
VOUT (V)
-
DETECTOR CELLS
OUTPUT BUFFER
OUT 7.2k VEE
8
0 -80 VCC = ENBL = 3V -60 -40 -20 0 INPUT POWER (dBm) 20
5537 TA01b
1
ENBL
BANDGAP REFERENCE AND BIASING EXPOSED PAD 9
7
5537 TA01a
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Output Voltage, Linearity Error vs Input Power at 200MHz
2.4 2.0 85C 1.6 1.2 0.8 0.4 -40C 25C 1 0 -1 -2 -3 3 2
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LINEARITY ERROR (dB)
LT5537
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW ENBL 1 IN+ 2 IN- 3 CAP+ 4 9 8 7 6 5 OUT VEE VCC CAP-
Power Supply Voltage ........................................... 5.5V Enable Voltage ................................... -0.2V, VCC + 0.2V Input Power (Note 2) ......................................... 22dBm Operating Ambient Temperature Range .. - 40C to 85C Storage Temperature Range ................ - 65C to 125C Maximum Junction Temperature ......................... 125C
DDB PACKAGE 8-LEAD (3mm 2mm) PLASTIC DFN
JA = 76C/W EXPOSED PAD (PIN 9) SHOULD BE SOLDERED TO PCB
ORDER PART NUMBER LT5537EDDB
DDB PART MARKING LBJR
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
PARAMETER Signal Input Input Frequency Range Maximum Input Power for Monotonic Output (Note 5)
VCC = 3V, ENBL = 3V, TA = 25C, unless otherwise specified. (Notes 3, 4)
MIN TYP 10 to 1000 14.0 11.6 9.4 VCC - 0.4 1.73k //1.45pF 88.8 72.5 19.6 -97 -76.7 -0.007 90.6 81.0 20 -96 -77.2 -0.005 dB dB mV/dB dBm dBm dB/C dB dB mV/dB dBm dBm dB/C MAX UNITS MHz dBm dBm dBm V
CONDITIONS
50 Termination 200MHz 600MHz 1GHz Measured at 200MHz 3dB Error 1dB Error R1 = 33k (Note 8) VOUT = 0V, Extrapolated (Notes 3, 7) PIN = -20dBm 3dB Error 1dB Error R1 = 33k (Note 8) VOUT = 0V, Extrapolated (Notes 3, 7) PIN = -20dBm
DC Common Mode Voltage Small-Signal Impedance f = 10MHz Linear Dynamic Range Slope Intercept Sensitivity Temperature Coefficient f = 50MHz Linear Dynamic Range Slope Intercept Sensitivity Temperature Coefficient
2
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LT5537
ELECTRICAL CHARACTERISTICS
PARAMETER f = 100MHz Linear Dynamic Range Slope Intercept Sensitivity Temperature Coefficient f = 200MHz Linear Dynamic Range Slope Intercept Sensitivity Temperature Coefficient f = 400MHz Linear Dynamic Range Slope Intercept Sensitivity Temperature Coefficient f = 600MHz Linear Dynamic Range Slope Intercept Sensitivity Temperature Coefficient f = 1GHz Linear Dynamic Range Slope Intercept Sensitivity Temperature Coefficient Output Starting Voltage Response Time Baseband Modulation Bandwidth Shutdown Mode ENBL = High (On) ENBL = Low (Off) ENBL Input Current Turn-On Time Turn-Off Time VENBL = 3V VENBL = 0V 3dB Error 1dB Error 3dB Error 1dB Error 3dB Error 1dB Error 3dB Error 1dB Error 3dB Error 1dB Error
VCC = 3V, ENBL = 3V, TA = 25C, unless otherwise specified. (Notes 3, 4)
MIN TYP 90.5 82.8 20.3 -95 -77 -0.004 90.3 83.5 21.2 -94 -76.4 0.010 88.2 70.8 23.1 -91 -75.3 0.019 85.8 72.5 25.2 -89 -74.1 0.026 63.5 51.7 31.4 -80 -69.2 0.031 0.4 110 6 1 0.3 100 0 100 100 MAX UNITS dB dB mV/dB dBm dBm dB/C dB dB mV/dB dBm dBm dB/C dB dB mV/dB dBm dBm dB/C dB dB mV/dB dBm dBm dB/C dB dB mV/dB dBm dBm dB/C V ns MHz V V A A s s
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CONDITIONS
R1 = 33k (Note 8) VOUT = 0V, Extrapolated (Notes 3, 7) PIN = -20dBm
R1 = 33k (Note 8) VOUT = 0V, Extrapolated (Notes 3, 7) PIN = -20dBm
R1 = 33k (Note 8) VOUT = 0V, Extrapolated (Notes 3, 7) PIN = -20dBm
R1 = 33k (Note 8) VOUT = 0V, Extrapolated (Notes 3, 7) PIN = -20dBm
R1 = 33k (Note 8) VOUT = 0V, Extrapolated (Notes 3, 7) PIN = -20dBm No RF Signal Present Input from -30dBm to 0dBm, CLOAD = 2.5pF Output Load Capacitance = 2.5pF
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LT5537
ELECTRICAL CHARACTERISTICS
PARAMETER Power Supply Supply Voltage Supply Current Shutdown Current (Note 6) VCC = 3V ENBL = Low
VCC = 3V, ENBL = 3V, TA = 25C, unless otherwise specified. (Notes 3, 4)
MIN 2.7 10 13.5 500 TYP MAX 5.25 15 UNITS V mA A
CONDITIONS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Maximum differential AC input voltage between IN+ and IN- is 4V peak. Equivalent to 22dBm with 50 input impedance or 16dBm with 200 input impedance (1:4 transformer used). Note 3: Tests are performed as shown in the configuration of Figure 13. Note 4: Specifications over the -40C to 85C temperature range are assured by design, characterization and correlation with statistical process control. Note 5: Operation at lower frequency is possible as described in the "Low Frequency Operation" section in Applications Information.
Note 6: The maximum output voltage is limited to approximately VCC - 0.6V. Either the output slope should be reduced or input power level should be limited in order to avoid saturating the output circuit when VCC < 3V. See discussion in "Dynamic Range" section. Note 7: Sensitivity is defined as the minimum input power required for the output voltage to be within 3dB of the ideal log-linear transfer curve. Sensitivity can be improved by as much as 10dB by using a narrowband input impedance transformation network. See discussion in "Input Matching" section. Note 8: The output slope is adjustable using an external pull-down resistor (R1). See Applications Information for description of the output circuit.
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
20 RF INPUT SIGNAL OFF ENBL = VCC ENBL CURRENT (A) TA = 85C 16 TA = 25C 14
18 SUPPLY CURRENT (mA)
12
10
2.5
3.0
4
UW
ENBL Current vs Supply Voltage
250 RF INPUT SIGNAL OFF ENBL = VCC
200 TA = 85C 150 TA = 25C TA = -40C 100
TA = -40C
50
3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5
5537 G02
2.5
3.0
3.5 4.0 4.5 SUPPLY VOLTAGE (V)
5.0
5.5
5537 G03
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LT5537 TYPICAL PERFOR A CE CHARACTERISTICS
Output Voltage, Linearity Error vs Input Power at 10MHz
2.4 2.0 25C 1.6 VOUT (V) -40C 1.2 0.8 0.4 0 -80 85C 0 -1 -2 -3 -60 -40 -20 0 INPUT POWER (dBm) 20
5537 G04
VCC = ENBL = 3V
VOUT VARIATION (dB)
0 -1 -2 -3 -80 85C
VOUT (V)
VOUT Variation vs Input Power at 50MHz
3 2 VOUT VARIATION (dB) 85C 1 0 -1 -2 -3 -80 -40C
VOUT (V)
1.6 1.2 0.8 0.4
NORMALIZED AT 25C VCC = ENBL = 3V
25C
VOUT VARIATION (dB)
-60
-40 -20 0 INPUT POWER (dBm)
Output Voltage, Linearity Error vs Input Power at 200MHz
2.4 2.0 85C 1.6
VOUT (V)
25C -40C
VOUT VARIATION (dB)
1.2 0.8 0.4
0 -1 -2
0 -1 -40C -2 -3 -80
VOUT (V)
0 -80
VCC = ENBL = 3V -60 -40 -20 0 INPUT POWER (dBm) 20
5537 G10
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20
5537 G07
VOUT Variation vs Input Power at 10MHz
3 2 LINEARITY ERROR (dB)
LINEARITY ERROR (dB)
Output Voltage, Linearity Error vs Input Power at 50MHz
2.4 2.0 85C 1.6 1.2 0.8 0.4 0 -80 25C VCC = ENBL = 3V 3 2 LINEARITY ERROR (dB) 1 0 -1 -2 -3 -60 -40 -20 0 INPUT POWER (dBm) 20
5537 G06
3 2 1
NORMALIZED AT 25C VCC = ENBL = 3V
1
-40C
-40C
-60
-40 -20 0 INPUT POWER (dBm)
20
5537 G05
Output Voltage, Linearity Error vs Input Power at 100MHz
2.4 2.0 85C 1 0 -1 -2 -3 -60 -40 -20 0 INPUT POWER (dBm) 20
5537 G08
VOUT Variation vs Input Power at 100MHz
3 2
VCC = ENBL = 3V
3 2 85C 1 0 -1 -40C -2 -3 -80
LINEARITY ERROR (dB)
NORMALIZED AT 25C VCC = ENBL = 3V
-40C
0 -80
-60
-40 -20 0 INPUT POWER (dBm)
20
5537 G09
VOUT Variation vs Input Power at 200MHz
3 2 1 3 2 85C 1 NORMALIZED AT 25C VCC = ENBL = 3V
Typical Detector Characteristics
2.4 2.0 1.6 1.2 0.8 0.4 0 -80 TA = 25C 200MHz ENBL = VCC
5V 3V
-3
-60
-40 -20 0 INPUT POWER (dBm)
20
5537 G11
-60
-20 -40 INPUT POWER (dBm)
0
20
5537 G12
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LT5537 TYPICAL PERFOR A CE CHARACTERISTICS
Output Voltage, Linearity Error vs Input Power at 400MHz
3.0 2.5 85C 25C 2.0 VOUT (V) 1.5 1.0 0.5 VCC = ENBL = 3V 0 -80 -60 -40 -20 0 INPUT POWER (dBm) -40C 1 0 -1 -2 -3 20
5537 G13
VOUT VARIATION (dB)
VOUT (V)
VOUT Variation vs Input Power at 600MHz
3 2 VOUT VARIATION (dB) 1 0 -1 -40C -2 -3 -80 0.5 NORMALIZED AT 25C VCC = ENBL = 3V 85C 2.0 3.0 2.5
VOUT VARIATION (dB)
VOUT (V)
-60
-40 -20 0 INPUT POWER (dBm)
Output Voltage Distribution vs Temperature at -50dBm
25 RF PIN = -50dBm at 200MHz VCC = ENBL = 3V 20 25C -40C 85C 25
DISTRIBUTION (%)
DISTRIBUTION (%)
15
10
5
0 0.8 0.825 0.85 0.875 0.9 0.925 0.95 0.975 1 OUTPUT VOLTAGE (V) 1.025 1.05 1.075 1.1
5537 G19
6
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20
5537 G16
VOUT Variation vs Input Power at 400MHz
3 2 LINEARITY ERROR (dB)
Output Voltage, Linearity Error vs Input Power at 600MHz
3.0 2.5 85C 25C 2.0 1.5 1.0 -40C 1 0 -1 -2 -3 20
5537 G15
3 2 85C 1 0 -1 -40C -2 -3 -80
NORMALIZED AT 25C VCC = ENBL = 3V
3 2 LINEARITY ERROR (dB)
0.5 VCC = ENBL = 3V 0 -80 -60 -40 -20 0 INPUT POWER (dBm)
-60
-40 -20 0 INPUT POWER (dBm)
20
5537 G11
Output Voltage, Linearity Error vs Input Power at 1GHz
3 2 3 2
VOUT Variation vs Input Power at 1GHz
NORMALIZED AT 25C VCC = ENBL = 3V 85C 1 0 -1 -40C -2 -3 -80
85C 25C
LINEARITY ERROR (dB)
1 0 -1 -2 -3 20
5537 G17
1.5 1.0
-40C
VCC = ENBL = 3V 0 -80 -60 -40 -20 0 INPUT POWER (dBm)
-60
-40 -20 0 INPUT POWER (dBm)
20
5537 G18
Output Voltage Distribution vs Temperature at -20dBm
RF PIN = -20dBm at 200MHz VCC = ENBL = 3V 20 25C -40C 85C
15
10
5
0 1.45 1.475 1.5 1.525 1.55 1.575 1.6 1.625 1.65 1.675 1.7 1.725 1.75 5537 G20 OUTPUT VOLTAGE (V)
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LT5537
PI FU CTIO S
ENBL (Pin 1): Enable Pin. When the input voltage is higher than 1V, the circuit is ON. When the input voltage is less than 0.3V, or this pin is not connected, the chip is disabled (OFF). IN+, IN- (Pins 2, 3): Differential Signal Input Pins. These pins are internally biased to VCC - 0.4V. The impedance between IN+ and IN- is approximately 1.73k//1.45pF at 200MHz. The input pins should be AC coupled. CAP+, CAP- (Pins 4, 5): External Filter Capacitor Pins. The minimum RF input frequency can be lowered by adding an optional external capacitor between CAP+ and CAP-. VCC (Pin 6): Power Supply Pin. This pin should be decoupled using 1000pF and 0.1F capacitors. VEE (Pin 7): Ground pin. OUT (Pin 8): Output pin. Exposed Pad (Pin 9): Should be connected to PCB ground.
BLOCK DIAGRA
2
IN
+
3
IN -
1
ENBL
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7k 7k
4 CAP+
5 CAP-
OFFSET CANCELLATION
VCC
6
DETECTOR CELLS
OUTPUT BUFFER
OUT 7.2k VEE
8
BANDGAP REFERENCE AND BIASING EXPOSED PAD 7
7
5537 BD
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LT5537
APPLICATIO S I FOR ATIO
The LT5537 provides a log-linear relationship between an RF/IF input voltage and its output. The input signal is amplified successively by limiting amplifier stages. A series of detector cells rectify the signals and produce an output current which is log-linearly related to the input power with a coefficient (ISLOPE) of 3.4A/dB at 200MHz (independent of the input termination impedance). This coefficient is almost constant below 200MHz, but rises at higher frequency. The normalized slope variation plot in Figure 1 can be used to determine the log-linear coefficient at any frequency. The slope of the output voltage curve is determined by the total load resistance at the output terminal. VSLOPE = ISLOPE * RLOAD The on-chip pull-down resistor is 7.2k. The total load resistance (RLOAD) can be adjusted by adding external load resistance to change the output slope. For example, to achieve a log-linear rate of 20mV/dB, a 33k resistor is connected between the output pin and ground. Slope = 3.4A/dB * (7.2//33)k = 20.1mV/dB Additionally, an off-chip capacitor may be used to reduce the output time domain voltage ripple.
% OF 3.4A/dB AT 200MHz
8
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150 140 130 120 110 100 90 80 70 60 50 1 50 100 200 400 600 1000 FREQUENCY (MHz)
5537 F01
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Figure 1. Slope Variation over Frequency
VCC
DETECTOR OUTPUT
8 7.2k
OUT
5537 F02
Figure 2. Simplified Output Circuit
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LT5537
APPLICATIO S I FOR ATIO
Dynamic Range
The LT5537 is capable of detecting and log-converting an input signal over a wide dynamic range. The range of the output voltage may be limited, however, and the monotonicity of the output versus input at high input level may be affected if the supply voltage is low and the log-linear slope is set too high. The minimum VCC to support 90dB dynamic range with 20mV/dB slope is 2.8V under nominal conditions at 25C. The data shown in the Typical Performance Characteristics plots was taken with VCC = 3V. If there is difficulty encountered in achieving the desired dynamic range, then the user is advised to increase the supply voltage or else to decrease the output slope by connecting a smaller valued resistor between the output and ground.
VCC CAP+ CAP- 7k IN+ IN-
5537 F04
7k
TO 2ND STAGE
VBIAS
Figure 3. Simplified Input Circuit
Figure 4. Input Admittance
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Input Matching The LT5537 has a high impedance input (Figure 3). The differential input impedance is derived from S11 measurement with one of the input pins AC grounded (Figure 4). At 200MHz, the input is equivalent to 1.73k//1.45pF (Table 1). The input dynamic range is constant in voltage terms, ranging from approximately -89dBVrms to 1dBVrms at 200MHz. The dynamic range expressed in power is dependent on the actual impedance selected in the application design.
Table 1. Parallel Equivalent RC of the LT5537 Input
FREQUENCY 100MHz 200MHz 400MHz 600MHz 800MHz 1000MHz R 1.85k 1.73k 1.07k 673 435 303 C 1.51pF 1.45pF 1.48pF 1.52pF 1.65pF 1.78pF
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The simplest way of input matching the LT5537 is to terminate the input signal with a 50 resistor and AC couple it to one of the input pins while AC grounding the other input pin (Figure 13). The sensitivity (defined as the minimum input power required for the output to be within 3dB of the ideal log-linear response) is -76.4dBm at 200MHz in this case. To achieve the best sensitivity, the input termination impedance should be increased and the input pins should be differentially driven. An example application circuit is shown in Figure 5 which uses a transformer to step up the impedance and perform the balun function. The 240 resistor (R2) sets the impedance at the input of the chip to 200. A 1:4 transformer is used to match the 50 signal source impedance to the circuit input impedance. C1 and C2 are DC blocking capacitors. This application circuit has a (3dB error) sensitivity of -82.4dBm at 200MHz.
J1 INPUT M/A-COM ETC4-1-2 C1 IN+ 2 N/C R2 240 C2
IN- 3
5537 F06
(1:4)
Figure 5. Differential Input Matching to 200
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LT5537
APPLICATIO S I FOR ATIO
The 1:4 input transformer can also be replaced with a narrow band discrete balun circuit using three components as shown in Figure 6. Capacitors C11, C12 and inductor L1 form a tank circuit having a transformer-like function over a narrow bandwidth. The increased powerto-voltage transformation and the narrower input passband serve to improve the sensitivity of the logarithmic detector. The resonant balun circuit using discrete components can be custom designed for a range of different input impedance or sensitivity requirements.
C11 J1 INPUT RS L1 C12 R2 C2 IN- 3
5537 F07
C1
IN+ 2 RIN
Figure 6. Input Matching Network
2.5 TA = 25C 200MHz VCC = ENBL = 3V BALUN 264 SINGLE ENDED 50
2.0
VOUT (V)
1.5
1.0
0.5
0 -100
Figure 7. Measured Output with RIN = 264
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Table 2. Matching Network Component Values for 200MHz Center Frequency
10dB RETURN SENSITIVITY LOSS BW (dBm) (MHz) -82.4 -86.1 55 18 C11, C12 (pF) 15 7.5 EFFECTIVE INPUT RESISTANCE () 264 828 L1 (nH) 82 120 R2 () 330 2k Q 2.1 3.9
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The examples given in Table 2 cover two different transformation ratios. The first one transforms single-ended 50 to differential 264. The VOUT vs PIN transfer curves in Figure 7 indicate that the input power range for linear logarithmic detection is shifted downward by 7dB with a sensitivity improvement of 6dB compared with a simple 50 termination. The input return loss is 30dB at the design frequency of 200MHz. Bandwidth for better than 10dB return loss is 55MHz. The second example has a higher Q of 3.9 and a corresponding transformed impedance of 828. The input power range for linear operation is shifted downward by 12dB with a sensitivity improvement of 10dB compared with a simple 50 termination. The input return loss is 25dB at the design frequency. Bandwidth for better than 10dB return loss is 18MHz.
-80
-40 -20 -60 INPUT POWER (dBm)
0
20
5537 F10
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LT5537
APPLICATIO S I FOR ATIO
AGILENT E4436B SIGNAL GENERATOR
RF OUT J1 J2
POWER DIVIDER
J3
RF1 RF2
MINICIRCUIT SPDT ZYSW-2-50DR RF IN
TTL 50 OUT
-30dB ATTENUATOR
HP33120A FUNCTION GENERATOR
SYNC
Baseband Response The unloaded bandwidth of the LT5537 output buffer is 10MHz. With 2.5pF loading, the output bandwidth is approximately 6MHz. The baseband response of the LT5537 was characterized with a pulsed RF input using the setup shown in Figure 8. The input to the LT5537 is a 200MHz CW RF signal switched between -30dBm and -60dBm at a rate of 600kHz. The output was connected to a FET probe (Fluke PM8943A, 10:1 tip) which has a capacitive loading of 2.5pF. The 10% to 90% rise and fall times are 109ns and 115ns, respectively. The input signal and output response are shown in Figure 9.
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J1
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-30dB ATTENUATOR
J2
POWER DIVIDER
J3
INPUT
LT5537 DEMO BOARD
OUTPUT
PM8943A FET PROBE 10:1
CH3 CH4
-6dB ATTENUATOR
TRIG
HP 83480A DIGITAL COMMUNICATIONS ANALYZER WITH HP 54751A ELECTRONIC PLUG-IN
5537 F14
Figure 8. Timing Test Setup
Figure 9. Response Time (-30dBm to -60dBm)
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LT5537
APPLICATIO S I FOR ATIO
Table 3. Application Design Examples
DESIGN NUMBER 1 2 3 4 INPUT POLE 8.5kHz 1.3MHz 20MHz 2.8kHz
C1, C2 15nF 100pF 5pF 47nF
C6 Open 33nF 390pF 2.2F
INTERNAL POLE 414kHz 740Hz 50kHz 10Hz
Bold = dominant pole
Low Frequency Operation Because the limiting amplifier stages of the LT5537 are DC coupled, the high overall gain requires DC offset control. The LT5537 has internal DC offset cancellation circuitry. The voltage at the output of the limiting amplifier is low-pass filtered, inverted and fed back to the input of the limiting amplifier. The DC cancellation also reduces the gain of the amplifier at low frequency. As a result, the LT5537 has a bandpass frequency response with a lower end determined by the bandwidth of the offset cancellation feedback loop. The equivalent circuit of the loop filter is shown in Figure 10. C1 and C2 are the external DC blocking capacitors of the differential inputs; C6 is an optional external filter capacitor which is in parallel with an on-chip filter capacitor (CINT = 60pF). For analysis purposes only, the values for C6 and the on-chip filter capacitor are doubled when a single-ended equivalent circuit is derived from a differential implementation.
5.5k 2 * C6
7k 2 * CINT
C1 OR C2
1.5k
RS/2
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Figure 10. Offset Cancellation Loop Filter
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DC REJECTION BW 1.13MHz 160kHz 10MHz 2kHz DC LOOP PM 75 84 60 57 LOWEST OPERATING FREQUENCY 1.13MHz 1.3MHz 20MHz 2.8kHz APPLICATIONS Minimal Component Count General Purpose HF, Fast Settling Very Low Frequency
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The optional capacitance (C6) placed between CAP + (Pin 4) and CAP- (Pin 5) together with the input DC blocking capacitors C1 and C2 are used to adjust the operating frequency range. The DC offset cancellation loop contains two poles and one zero (in the low frequency region for the purpose of this analysis). The loop filter capacitance (C6 + CINT) generates one of the two poles, the input AC coupling capacitors (C1 and C2) determine the other pole and the input termination resistance leads to the zero. (The pole associated with the input AC coupling capacitor also sets the lower corner frequency of the signal path). The presence of the two poles in the circuit enables two approaches to the design of the application circuit for a desired frequency response. But stability margin has to be ensured in order to avoid ringing in response to any input transient. Table 3 lists four low frequency loop designs suitable for different applications. Design 1 is the simplest application circuit. The external capacitor C6 is not used. The input pole is set by the AC coupling capacitors (C1, C2) and is the dominant pole at 8.5kHz. The zero generated by the input coupling capacitor and the termination resistor is at 60 times the input pole frequency. The second pole set by the on-chip filter capacitor (CINT) should be at approximately the same frequency as that of the zero. This design has a stability phase margin (PM) of 75 degrees.
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LT5537
APPLICATIO S I FOR ATIO
Design 2 is the application circuit (Figure 13) used for characterization in this data sheet. This is a robust general purpose design which can operate as low as 1.3MHz. Optional filter capacitor (C6 = 33nF) together with the onchip capacitor set the dominant pole at 740Hz. The input pole associated with the AC coupling capacitors (C1, C2 = 100pF) is at 1.3MHz which is beyond the loop cut-off frequency of 160kHz. The zero is at an even higher frequency and can be safely ignored. This design has a stability phase margin of 84 degrees, resulting in a very well damped response to any input biasing transients. Design 3 features fast settling. This design is appropriate when fast response in the presence of input biasing transients is required, and very low frequency operation is not needed. Design 4 demonstrates the possibility of operating the LT5537 at very low frequency (<10kHz) by configuring the offset cancellation loop for very low bandwidth. The response of this circuit at 10kHz is plotted in Figure 11.
2.5 TA = 25C VCC = ENBL = 3V 2.0
VOUT (V)
1.5
1.0
0.5
0 -100
-80
-60 -40 -20 INPUT POWER (dBm)
0
20
5537 F17
Figure 11. 10kHz Operation
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Offset Cancellation Loop and the Timing Response The input of the LT5537 is AC coupled, and the on-chip DC biasing is automatically regulated as described above. But if the DC component of the input signal has any transient step with sufficiently short rise or fall time (for example the output of an active RF switch has a biasing shift between switching states), a transient voltage pulse is induced by the displacement current needed to charge the input AC coupling capacitor. Also, if the pulse frequency or the repetition rate is within the loop bandwidth of the offset cancellation circuit, the LT5537 will respond to the induced voltage pulse in the same way it nulls out its internal DC offset, even though the chip is DC isolated from the input signal. If the external capacitor (C6) is used to extend the low frequency response of the LT5537, then this will also lengthen the response time of the DC offset cancellation circuit. In the presence of DC steps or glitches at the input, the transient response of the slowed offset cancellation loop will be superimposed on the faster logarithmic detector output, degrading the overall response time of the chip. The sensitivity of the LT5537 is very high. An input biasing step with amplitude of 0.5mV can generate a output voltage response of 400mV before the input voltage transient dissipates or the offset cancellation loop nulls out the transient, whichever occurs first. One way to prevent the input signal containing a biasing transient from degrading the timing response is to design the offset cancellation loop to have a high bandwidth, allowing faster settling. Design 3 in Table 3 is suitable for this purpose, but will not operate below 20MHz.
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LT5537
APPLICATIO S I FOR ATIO
Enable Pin Operation
The enable circuit of the LT5537 is shown in a simplified form in Figure 12. When the voltage at the ENBL pin is 1V, the enable circuit biases the chip up for normal operation. The current drawn by the ENBL pin is dependent on the voltage on that pin. At VCC = ENBL = 3V, the ENBL current is typically 100A. At VCC = ENBL = 5V, the ENBL current increases to about 200A. When the voltage at the ENBL pin is 0.3V, or if the pin is not connected, the chip is disabled and draws a reduced supply current of about 500A, with VCC = 3V.
C1 100pF R2 51 C2 100pF LT5537 1 2 ENBL
EXPOSED PAD
INPUT
Figure 13. Application Board Schematic
Figure 14. Layout of the Evalulation Board
14
U
ENBL 25k
5537 F04
W
UU
Figure 12. Equivalent ENBL Input Circuit
ENBL 8 7 R1 33k VCC C3 1nF C4 1F
OUT VEE
OUTPUT
IN+ IN- CAP
+
3 4
VCC CAP
6
-5
5537 F19
C6 33nF
5537fa
LT5537
PACKAGE DESCRIPTIO U
DDB Package 8-Lead Plastic DFN (3mm x 2mm)
(Reference LTC DWG # 05-08-1702)
3.00 0.10 (2 SIDES) 0.675 0.05 2.50 0.05 1.15 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.20 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 BAR TOP MARK (SEE NOTE 6) 2.00 0.10 (2 SIDES) R = 0.115 TYP 5 0.56 0.05 (2 SIDES) 0.38 0.10 8 0.200 REF 0.75 0.05 4 0.25 0.05 2.15 0.05 (2 SIDES) BOTTOM VIEW--EXPOSED PAD 1 PIN 1 CHAMFER OF EXPOSED PAD
(DDB8) DFN 1103
0.61 0.05 (2 SIDES)
0.50 BSC
0 - 0.05
5537fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT5537 RELATED PARTS
PART NUMBER DESCRIPTION Infrastructure LT5511 LT5512 LT5514 LT5515 LT5516 LT5517 LT5519 LT5520 LT5521 LT5522 LT5524 LT5525 LT5526 LT5527 LT5528 High Linearity Upconverting Mixer DC-3GHz High Signal Level Downconverting Mixer Ultralow Distortion, IF Amplifier/ADC Driver with Digitally Controlled Gain 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator 0.8GHz to 1.5GHz Direct Conversion Quadrature Demodulator 40MHz to 900MHz Quadrature Demodulator RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer DC to 3GHz, 17dBm IIP3, Integrated LO Buffer 850MHz Bandwidth, 47dBm OIP3 at 100MHz, 10.5dB to 33dB Gain Control Range 20dBm IIP3, Integrated LO Quadrature Generator 21.5dBm IIP3, Integrated LO Quadrature Generator 21dBm IIP3, Integrated LO Quadrature Generator COMMENTS
0.7GHz to 1.4GHz High Linearity Upconverting Mixer 17.1dBm IIP3 at 1GHz, Integrated RF Output Transformer with 50 Matching, Single-Ended LO and RF Ports Operation 1.3GHz to 2.3GHz High Linearity Upconverting Mixer 15.9dBm IIP3 at 1.9GHz, Integrated RF Output Transformer with 50 Matching, Single-Ended LO and RF Ports Operation 10MHz to 3700MHz High Linearity Upconverting Mixer 400MHz to 2.7GHz High Signal Level Downconverting Mixer 24.2dBm IIP3 at 1.95GHz, NF = 12.5dB, 3.15V to 5.25V Supply, Single-Ended LO Port Operation 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports
Low Power, Low Distortion ADC Driver with Digitally 450MHz Bandwidth, 40dBm OIP3, 4.5dB to 27dB Gain Control Programmable Gain High Linearity, Low Power Downconverting Mixer High Linearity, Low Power Downconverting Mixer 400MHz to 3.7GHz High Linearity, Downconverting Mixer 1.5GHz to 2.4GHz High Linearity Direct I/Q Modulator 800MHz to 2.7GHz RF Measuring Receiver RF Power Detectors with >40dB Dynamic Range 100kHz to 1000MHz RF Power Detector 300MHz to 7GHz RF Power Detector 300MHz to 3GHz RF Power Detector 300MHz to 7GHz Precision RF Power Detector 300MHz to 7GHz Precision RF Power Detector 300MHz to 7GHz Precision RF Power Detector 50MHz to 3GHz RF Power Detector with 60dB Dynamic Range Precision 600MHz to 7GHz RF Detector with Fast Comparator Output 500MHz Quadrature Demodulator with VGA and 17MHz Baseband Bandwidth 12-Bit, 80Msps 14-Bit, 80Msps Single-Ended 50 RF and LO Ports, 17.6dBm IIP3 at 1900MHz, ICC = 28mA 3V to 5.3V Supply, 16.5dBm IIP3, 100kHz to 2GHz RF, NF = 11dB, ICC = 28mA, -65dBm LO-RF Leakage 23.5dBm IIP3, 12.5dB NF at 1.9GHz, 50 Single-Ended RF and LO Ports 21.8dBm OIP3 at 2GHz, -159dBm/Hz Noise Floor, 50 Interface at All Ports
RF Power Detectors LT5504 LTC 5505 LTC5507 LTC5508 LTC5509 LTC5530 LTC5531 LTC5532 LT5534 LTC5536
(R)
80dB Dynamic Range, Temperature Compensated, 2.7V to 5.25V Supply 300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply 100kHz to 1GHz, Temperature Compensated, 2.7V to 6V Supply 44dB Dynamic Range, Temperature Compensated, SC70 Package 36dB Dynamic Range, Low Power Consumption, SC70 Package Precision VOUT Offset Control, Shutdown, Adjustable Gain Precision VOUT Offset Control, Shutdown, Adjustable Offset Precision VOUT Offset Control, Adjustable Gain and Offset 1dB Output Variation over Temperature, 38ns Response Time 25ns Response Time, Comparator Reference Input, Latch Enable Input, -26dBm to +12dBm Input Range 17MHz Baseband Bandwidth, 40MHz to 500MHz IF, 1.8V to 5.25V Supply, -7dB to 56dB Linear Power Gain 500MHz BW S/H, 71.8dB SNR 500MHz BW S/H, 75.5dB SNR
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Low Voltage RF Building Block LT5546
Wide Bandwidth ADCs LTC1749 LTC1750
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 0306 REV A * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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